id string | difficulty string | is_agentic string | instruction string | targets list | dut_module_name string | dut_instance_name string | rtl_files list | spec_files list |
|---|---|---|---|---|---|---|---|---|
cvdp_agentic_byte_enable_ram_0004 | medium | Agentic | I have a specification of a custom_byte_enable_ram module in the docs directory. Write a SystemVerilog testbench `tb_custom_byte_enable_ram.sv` in the verif directory to apply stimulus and achieve maximum coverage for the `custom_byte_enable_ram` module.
Include the following in the generated testbench:
**Module Inst... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | custom_byte_enable_ram | uut | [
{
"name": "custom_byte_enable_ram.sv",
"content": "module custom_byte_enable_ram \n #(\n parameter XLEN = 32,\n parameter LINES = 8192\n )\n (\n input logic clk,\n input logic[$clog2(LINES)-1:0] addr_a,\n input logic en_a,\n input logic[XLEN... | [
{
"name": "specs.md",
"content": "# Custom Byte-Enable RAM Module\n\nThis module implements a dual-port RAM with byte-enable support and pipelining, designed for efficient memory operations in systems such as processors or embedded controllers. It features separate interfaces for two independent ports (Port... |
cvdp_copilot_hamming_code_tx_and_rx_0031 | easy | Non-Agentic | Create a testbench to only supply stimulus to a `hamming_code_receiver` module. This module decodes an 8-bit input signal and detects single-bit errors using Hamming code principles. The receiver performs "even parity checks" to identify single-bit errors in `data_in` and provides corrected 4-bit data through the outpu... | [
{
"inst_name": "uut_receiver",
"metric": "Overall Average",
"target_percentage": 100
}
] | hamming_code_receiver | uut_receiver | [
{
"name": "hamming_code_receiver.sv",
"content": "module hamming_code_receiver (\n input[7:0] data_in,\n output [3:0] data_out\n);\n \n wire c1,c2,c3,error;\n reg[7:0] correct_data;\n \n \n assign c3 = data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[7];\n assign c2 = data_in[2] ^ data_in[3] ^ data_in... | [] |
cvdp_copilot_simple_spi_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `spi_fsm`. The module handles data transmission in a serial format from a 16-bit input vector (`i_data_in`) using an SPI protocol. The design includes proper state transitions, signal handling, and timing synchronization to ensure accurate data transmissio... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 94
}
] | spi_fsm | dut | [
{
"name": "spi_fsm.v",
"content": "module spi_fsm (\n input wire i_clk, // System clock\n input wire i_rst_b, // Active-low async reset\n input wire [15:0] i_data_in, // Parallel 16-bit data to transmit\n input wire i_enable, // Enable block\n input... | [] |
cvdp_copilot_word_reducer_0012 | easy | Non-Agentic | Create a testbench named `tb_Bit_Difference_Counter` using SystemVerilog to generate stimulus for the `Bit_Difference_Counter` module, which calculates the hamming distance (bitwise difference) between two inputs of equal bit width. The testbench should apply edge-case scenarios and random input patterns to thoroughly ... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | Bit_Difference_Counter | dut | [
{
"name": "Data_Reduction.sv",
"content": "`timescale 1ns / 1ps\n\nmodule Bit_Difference_Counter\n#(\n parameter BIT_WIDTH = 3, // Defines the width of the input vectors.\n localparam COUNT_WIDTH = $clog2(BIT_WIDTH + 1) // Calculates the width required to represent th... | [] |
cvdp_agentic_ttc_lite_0007 | hard | Agentic | I have a specification of a `ttc_counter_lite` module in the `docs` directory. Write a SystemVerilog TB `ttc_counter_lite_tb.sv` in the `verif` directory to only generate stimuli and achieve maximum functional coverage for the `ttc_counter_lite` module.
Include the following in the generated testbench:
- **Module Ins... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | ttc_counter_lite | dut | [
{
"name": "ttc_counter_lite.sv",
"content": "`timescale 1ns / 1ps\nmodule ttc_counter_lite (\n input wire clk, // Clock signal\n input wire reset, // Reset signal\n input wire [3:0] axi_addr, // AXI address for read/write\n input wire [3... | [
{
"name": "specification.md",
"content": "# ttc_counter_lite Specification Document\n\n## Introduction\n\nThe **ttc_counter_lite** module implements a lightweight, programmable timer with support for **interval and single-shot counting modes**. It includes a 16-bit up-counter, configurable match and reload ... |
cvdp_copilot_bcd_adder_0007 | easy | Non-Agentic | Create a testbench to generate stimulus for the `bcd_adder` module, which performs Binary Coded Decimal (BCD) addition on two 4-bit inputs, a and b.
## Testbench Description
### Inputs
- Registers: a and b are 4-bit registers that provide the two BCD numbers to be added.
### Outputs
- The outputs from the BCD adder... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | bcd_adder | uut | [
{
"name": "bcd_adder.sv",
"content": "module bcd_adder( \n input [3:0] a, // 4-bit BCD input\n input [3:0] b, // 4-bit BCD input\n output [3:0] sum, // The corrected 4-bit BCD result of the addition\n ... | [] |
cvdp_copilot_apb_history_shift_register_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `APBGlobalHistoryRegister`. The register updates synchronously on every gated rising edge of the `history_shift_valid` clock, shifting in predicted outcomes or restoring history on mispredictions. The test bench should systematically generate input vectors... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | APBGlobalHistoryRegister | dut | [
{
"name": "APBGlobalHistoryRegister.v",
"content": "module APBGlobalHistoryRegister (\n // APB clock & reset\n input wire pclk,\n input wire presetn, // Active-low reset\n\n // APB signals\n input wire [9:0] paddr,\n input wire pselx,\n input wire ... | [] |
cvdp_copilot_ring_token_0004 | easy | Non-Agentic | Create a SystemVerilog testbench module named **`tb_token_ring_fsm`** that instantiates the `token_ring_fsm` module as the Unit Under Test (UUT). The testbench must include a **stimulus generator** that systematically drives various input conditions to achieve **100% code and functional coverage** for the `token_ring_f... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | token_ring_fsm | uut | [
{
"name": "token_ring_fsm.sv",
"content": "module token_ring_fsm (\n input logic clk, // Clock input\n input logic rst, // Reset input\n input logic [3:0] data_in, // Data input from node\n output reg [3:0] data_out, // Data output to node\n input logic has_dat... | [] |
cvdp_copilot_morse_code_0027 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench `morse_encoder_tb`. The testbench must instantiate the `morse_encoder` **RTL** module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `morse_encoder` module converts an **8-bit ASCII input... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | morse_encoder | dut | [
{
"name": "morse_encoder.sv",
"content": "module morse_encoder (\n input wire [7:0] ascii_in, // ASCII input character\n output reg [5:0] morse_out, // Morse code output \n output reg [3:0] morse_length // Length of the Morse code sequence\n);\n\n always @(*) begin\n case (a... | [] |
cvdp_copilot_restoring_division_0006 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module generates the output `quotient`, `remainder`, and `valid` once the computation is completed for the given `dividend` and `divisor` when the `start` signa... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\n\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start signal to b... | [] |
cvdp_copilot_restoring_division_0034 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module produces the `quotient`, `remainder`, and asserts the `valid` signal upon computation completion. Additionally, it sets the `divisor_valid_result` flag t... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start s... | [] |
cvdp_copilot_microcode_sequencer_0028 | medium | Non-Agentic | Complete the given partial System Verilog Testbench `tb_microcode_sequencer`.The testbench must instantiate the `microcode_sequencer` RTL module and provide input stimulus for it, apply various input combinations representing different instructions and conditions such as resetting, fetching instructions, loading data, ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | microcode_sequencer | uut | [
{
"name": "microcode_sequencer.sv",
"content": "module microcode_sequencer (\n // Inputs\n input logic clk, // Input Clock\n input logic c_n_in, // Input Carry for Carry Lookahead Adder\n input logic c_inc_in, // Input Carry for Carry Lookahead Program Counter Incrementer\n input logic r_en, // A... | [] |
cvdp_agentic_async_fifo_compute_ram_application_0004 | medium | Agentic | Create a test bench in SystemVerilog for a Verilog module named `async_fifo`. The **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory and Gray-coded pointe... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Assertion",
"target_percentage": 100
},
{
"inst_name": "dut",
"metric": "Toggle",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Block",... | async_fifo | dut | [
{
"name": "async_fifo.sv",
"content": "module async_fifo\n #(\n parameter p_data_width = 32, // Parameter to define the width of the data\n parameter p_addr_width = 16 // Parameter to define the width of the address\n )(\n input wire i_wr_clk, // Write ... | [
{
"name": "fifo.md",
"content": "# Asynchronous FIFO Specification\n\n## 1. Overview\n\nThe **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory... |
cvdp_copilot_gaussian_rounding_div_0014 | easy | Non-Agentic | Write a testbench to only generate stimulus for a `divider` that performs non-restoring division for two unsigned positive integer inputs, and generates the output `quotient`, `remainder` and `valid` when computation is completed for the inputs `dividend` and `divisor` when `start` is asserted. In this design, the outp... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | divider | dut | [
{
"name": "divider.sv",
"content": "`timescale 1ns/1ps\nmodule divider #\n(\n parameter WIDTH = 32\n)\n(\n input wire clk,\n input wire rst_n, // Active-low asynchronous reset\n input wire start, // Start signal for new operation\n ... | [] |
cvdp_copilot_prim_max_0005 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `prim_max_find` module. This module implements a **binary tree-based maximum value finder** that determines the highest value from multiple input sources and provides the corresponding index. The testbench must apply a range of test cases to validate correct maximum v... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 96
}
] | prim_max_find | dut | [
{
"name": "prim_max_find.sv",
"content": "module prim_max_find #(\n parameter int NumSrc = 8,\n parameter int Width = 8,\n // Derived parameters\n localparam int SrcWidth = $clog2(NumSrc),\n localparam int NumLevels = $clog2(NumSrc),\n localparam int NumNodes = 2**(NumLevels+1)-1\n) (\n input ... | [] |
cvdp_copilot_manchester_enc_0009 | easy | Non-Agentic | Complete the given SystemVerilog testbench for the `top_manchester` module. The testbench currently instantiates the UUT and should include stimulus generation logic that dynamically produces a wide range of test scenarios to ensure 100% functional and code coverage. The stimulus generation logic should drive the desig... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | top_manchester | uut | [
{
"name": "top_manchester.sv",
"content": "module top_manchester #(\n parameter N = 8 // Default width of input and output data\n) (\n input logic clk_in, // Clock input\n input logic rst_in, // Active high reset input\n \n // Encoder Signals\n inpu... | [] |
cvdp_agentic_nbit_swizzling_0005 | easy | Agentic | I have a specification of a `nbit_swizzling` module in the `docs` directory. Write a system verilog testbench `nbit_swizzling_tb.sv` in the verif directory to only generate stimulus and achieve maximum coverage for the `nbit_swizzling` module.
Include the following in the generated testbench:
1. **Module instance:**
... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | nbit_swizzling | dut | [
{
"name": "nbit_swizzling.sv",
"content": "`timescale 1ns/1ps\nmodule nbit_swizzling #(parameter DATA_WIDTH = 64)(\n input [DATA_WIDTH-1:0] data_in, // Input data of size DATA_WIDTH \n input [1:0] sel, \t // 2-b... | [
{
"name": "nbit_swizzling_spec.md",
"content": "The `nbit_swizzling` module performs bit rearrangement **(swizzling)** and **Gray code** conversion on an input data bus of variable width. The module offers four swizzling patterns controlled by a **2-bit selection signal**. After the swizzling operation, an ... |
cvdp_copilot_gf_multiplier_0047 | medium | Non-Agentic | Create a testbench to generate stimuli for the `gf_mac` module, which computes a byte-wide Galois Field (2<sup>8</sup>) multiply-accumulate function over two `WIDTH`-bit inputs (`a` and `b`). The module also supports a passthrough mode and provides status signals for validity, readiness, and error indication.
---
## D... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | gf_mac | uut | [
{
"name": "gf_mac.sv",
"content": "`timescale 1ns/1ps\nmodule gf_mac#(parameter WIDTH=32)(\n input reset,\n input enable,\n input pass_through,\n input [WIDTH-1:0] a,\n input [WIDTH-1:0] b,\n output [7:0] result,\n output valid_result,\n output ready,\n output error_flag\n);\n ... | [] |
cvdp_copilot_encoder_8b10b_0026 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_encoder_8b10b` that instantiates the `encoder_8b10b` module as the Unit Under test (UUT). This testbench module must include the `stimulus generation` logic only, which systematically drives different input conditions to the `encoder_8b10b` module to achieve **100% func... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | encoder_8b10b | uut | [
{
"name": "encoder_8b10b.sv",
"content": "module encoder_8b10b (\n input logic clk_in, // Trigger on rising edge\n input logic reset_in, // Reset, assert HI\n input logic control_in, // Control character, assert HI for control words\n input logic ... | [] |
cvdp_copilot_traffic_light_controller_0007 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `traffic_controller_fsm`. Based on sensor inputs and timing signals, the FSM manages the traffic lights for both a main road and a side road. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to ... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | traffic_controller_fsm | dut | [
{
"name": "traffic_light_controller.sv",
"content": "module traffic_controller_fsm ( \n input i_clk, // System clock input\n input i_rst_b, // Active-low reset signal\n input i_vehicle_sensor_input, // High when a vehicle is present on the side road\n in... | [] |
cvdp_copilot_thermostat_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `thermostat`. It automatically switches between heating and cooling based on temperature feedback. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible covera... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | thermostat | dut | [
{
"name": "thermostat.v",
"content": "module thermostat (\n input wire [5:0] i_temp_feedback, // Temperature feedback bits\n input wire i_fan_on, // Manual fan control\n input wire i_enable, // Enable thermostat\n input wire i_fault, // Fault signal\n inpu... | [] |
cvdp_copilot_apb_dsp_unit_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `apb_dsp_unit`. The module serves as an APB interface for configuring internal registers. These registers specify which memory addresses are used for arithmetic operations (addition or multiplication). The computed result is then made available through a d... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | apb_dsp_unit | dut | [
{
"name": "apb_dsp_unit.v",
"content": "module apb_dsp_unit (\n // APB clock & reset\n input wire pclk,\n input wire presetn, // Active-low reset\n\n // APB signals\n input wire [9:0] paddr,\n input wire pselx,\n input wire penable,\n input wi... | [] |
cvdp_copilot_vending_machine_0006 | medium | Non-Agentic | Complete the given partial SystemVerilog testbench `serial_line_code_converter_tb`. The testbench must instantiate the `serial_line_code_converter` RTL module and provide input stimulus for various testcases. This testbench simulates a vending machine that processes item selection, coin insertion, item dispensing, chan... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | vending_machine | uut | [
{
"name": "vending_machine.sv",
"content": "module vending_machine(\n input clk, // Clock signal\n input rst, // Reset signal\n input item_button, // Signal for item selection button press (active high, rising edge)\n input [2:0]... | [] |
cvdp_agentic_lfsr_0018 | medium | Agentic | I have a documentation `docs/8Bit_lfsr_spec.md` for the `lfsr_8bit` module. Write a SystemVerilog testbench `tb_lfsr_8bit.sv` in the verif directory that generates stimulus to thoroughly test and achieve maximum functional coverage for the `lfsr_8bit` module.
___
### The interface of `lfsr_8bit` RTL module is given bel... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 85
}
] | lfsr_8bit | uut | [
{
"name": "lfsr_8bit.sv",
"content": "`timescale 1ns / 1ps\n\nmodule lfsr_8bit (\n input clock,\n input reset,\n input [7:0] lfsr_seed,\n input sel, // Selector for NAND or NOR operation (0: NOR for more 0s, 1: NAND for more 1s)\n input dir, // Direction control (0: LSB to MSB, 1: MSB to LS... | [
{
"name": "8Bit_lfsr_spec.md",
"content": "# **Specification Document: 8-bit LFSR with Configurable Feedback, Direction, and Weighted Logic**\n\n## **1. Introduction**\nThis document describes the design and implementation of a **8-bit Linear Feedback Shift Register (LFSR)** using the **Galois configuration... |
cvdp_copilot_static_branch_predict_0035 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_static_branch_predict` that instantiates the `static_branch_predict` module as the Unit Under Test (UUT). The testbench must include a stimulus generator that systematically drives various input conditions to achieve a minimum of 95% code and functional coverage for the... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | static_branch_predict | uut | [
{
"name": "static_branch_predict.sv",
"content": "module static_branch_predict (\n \n // Instruction from fetch stage\n input logic [31:0] fetch_rdata_i,\n input logic [31:0] fetch_pc_i,\n input logic [31:0] register_addr_i,\n input logic fetch_valid_i,\n\n // Prediction for supplied instr... | [] |
cvdp_copilot_apb_dsp_op_0006 | medium | Non-Agentic | Create a SystemVerilog test bench for a module named `apb_dsp_op`. The test bench should systematically generate input vectors, apply them to the design under test (DUT), and aim to achieve 100% coverage.
---
## Instantiation
Name the instance of the RTL as **apb_dsp_op_dut**.
## **RTL Interface and Parameters**
| ... | [
{
"inst_name": "apb_dsp_op_dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | apb_dsp_op | apb_dsp_op_dut | [
{
"name": "apb_dsp_op.sv",
"content": "// APB DSP Operation Module\nmodule apb_dsp_op #(\n parameter ADDR_WIDTH = 'd8,\n parameter DATA_WIDTH = 'd32\n) (\n input logic clk_dsp, // Faster clock to DSP operation\n input logic en_clk_dsp, // Enable DSP operati... | [] |
cvdp_copilot_Serial_Line_Converter_0006 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench `serial_line_code_converter_tb`. The testbench must instantiate the `serial_line_code_converter` RTL module and provide input stimulus to validate its functionality. This module implements various serial line coding techniques. The testbench should include different in... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | serial_line_code_converter | dut | [
{
"name": "serial_line_code_converter.sv",
"content": "module serial_line_code_converter #(parameter CLK_DIV = 16)(\n input logic clk, // System clock\n input logic reset_n, // Active-low reset\n input logic serial_in, // Serial input signal\n input logic [2:0] mode... | [] |
cvdp_copilot_write_through_data_direct_mapped_cache_0001 | medium | Non-Agentic | Complete the given partial System Verilog Testbench `tb_ddm_cache`.The testbench must instantiate the `ddm_cache` RTL module and provide input stimulus for it, focusing exclusively on generating comprehensive test vectors rather than building a full testbench. The data cache handles read and write operations from the C... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 85
}
] | ddm_cache | dut | [
{
"name": "ddm_cache.sv",
"content": "module ddm_cache (\n input logic clk, // Posedge clock\n input logic rst_n, // Asynchronous Negedge reset\n input logic [31:0] cpu_addr, // Memory address emitted by the CPU\n input logic [31:0] cpu_dout, // Data emitted... | [] |
cvdp_copilot_events_to_apb_0021 | medium | Non-Agentic | Write a SystemVerilog testbench named `tb_apb_controller` that only generates stimuli for an `apb_controller` module. The testbench should generate input stimuli for different operating conditions and sequences, including the handling of multiple simultaneous events (Event A, Event B, and Event C), proper prioritizatio... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | apb_controller | dut | [
{
"name": "apb_controller.sv",
"content": "module apb_controller(\n input logic clk, // Clock signal\n input logic reset_n, // Active low asynchronous reset signal\n input logic select_a_i, // Select signal for event A\n input logic ... | [] |
cvdp_copilot_afi_ptr_0004 | medium | Non-Agentic | Write a SystemVerilog testbench to only generate stimulus for a `cmprs_afi_mux_ptr_tb` module is responsible for managing pointer updates for multiple channels in a memory compression system. It handles resetting pointers, arbitrating between competing channels, and updating pointers based on increments while ensuring ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | cmprs_afi_mux_ptr | uut | [
{
"name": "cmprs_afi_mux_ptr.sv",
"content": "`timescale 1ns / 1ps\n\nmodule cmprs_afi_mux_ptr(\n input hclk, // Clock signal\n input reset, // Synchronous reset input\n input [26:0] sa_len_di, /... | [] |
cvdp_agentic_dual_port_memory_0012 | medium | Agentic | The `dual_port_memory` module's `specification.md` is in the `docs` folder. Write a SystemVerilog testbench `tb_dual_port_memory.sv` in the `verif` directory to generate **only stimulus** for the `dual_port_memory` module to achieve **maximum coverage** of the DUT.
---
### Include the Following:
#### **1. Module In... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | dual_port_memory | dut | [
{
"name": "dual_port_memory.sv",
"content": "module dual_port_memory #(\n parameter DATA_WIDTH = 4, // Data width\n parameter ECC_WIDTH = 3, // ECC bits for Hamming(7,4)\n parameter ADDR_WIDTH = 5, // Address width\n parameter MEM_DEPTH = (1 << ADDR_WIDTH)... | [
{
"name": "specification.md",
"content": "## Introduction\n\nThe `tb_dual_port_memory` testbench is designed to verify the functionality and robustness of a **dual-port memory module with ECC (Hamming code)**. The memory module features independent read and write ports (`addr_a`, `addr_b`) and ECC-based err... |
cvdp_copilot_perceptron_0018 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_perceptron_gates` that instantiates the `perceptron_gates` module as the Unit Under Test (UUT). The testbench must include a stimulus generator only that systematically drives various input conditions to achieve a minimum of 80% code and functional coverage for the `per... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | perceptron_gates | uut | [
{
"name": "perceptron_gates.sv",
"content": "`timescale 1ns/1ps\nmodule perceptron_gates (\n input logic clk,// Posedge clock\n input logic rst_n,// Negedge reset\n input logic signed [3:0] x1, // First Input of the Perceptron\n input logic signed [3:0] x2, // Second Input of the Perceptron\... | [] |
cvdp_agentic_queue_0007 | easy | Agentic | I have a specification for the `queue` module in the `docs` directory (`specification.md`). Write a SystemVerilog testbench `tb_queue.sv` in the `verif` directory to generate a stimulus for the `queue` module.
Include the following in the generated testbench:
---
### 1. **Module Instance:**
- Instantiate the `queue`... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | queue | dut | [
{
"name": "queue.sv",
"content": "module queue #(\n parameter DEPTH = 4,\n parameter DBITS = 32,\n parameter ALMOST_EMPTY_THRESHOLD = 1,\n parameter ALMOST_FULL_THRESHOLD = 4\n) (\n input logic rst_ni, // async, active-low reset\n input logic ... | [
{
"name": "specs.md",
"content": "# Queue Module Description\n\nThis module implements a parameterized fall-through queue that stores a configurable number of data words. It features a first-word-fall-through behavior where, upon a read, the next valid data element immediately appears at the output. The que... |
cvdp_copilot_binary_to_BCD_0030 | easy | Non-Agentic | Create a testbench for `binary_to_bcd` module, which converts an 8-bit binary input into a 12-bit BCD output using the Double Dabble algorithm, ensuring correct shifting, adjustment, and final conversion while validating that each BCD digit remains within the valid range (0-9). The testbench must have the instantiation... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | binary_to_bcd | uut | [
{
"name": "binary_to_bcd.sv",
"content": "`timescale 1ns / 1ps\n\nmodule binary_to_bcd (\n input logic [7:0] binary_in, // 8-bit binary input\n output logic [11:0] bcd_out // 12-bit BCD output (3 digits)\n);\n\n // Intermediate shift register to hold binary and BCD values\n logic [19:0] shift_reg;... | [] |
cvdp_copilot_binary_search_tree_sorting_0030 | medium | Non-Agentic | Implement a System Verilog testbench named `binary_search_tree_search_node_tb` to generate stimuli for a `search_binary_search_tree` module that performs a search for a given key in a binary search tree (BST).
## Design Specification:
The BST is a structure formed where each node contains a key, with its `left_child... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 96
}
] | search_binary_search_tree | dut | [
{
"name": "search_binary_search_tree.sv",
"content": "module search_binary_search_tree #(\n parameter DATA_WIDTH = 16, // Width of the data\n parameter ARRAY_SIZE = 15 // Maximum number of elements in the BST\n) (\n\n input clk, // Clock signal\n input re... | [] |
cvdp_copilot_binary_search_tree_sorting_0015 | medium | Non-Agentic | Write a SystemVerilog testbench named `bst_sort_tb` that generates only stimulus for a binary search tree (BST) based sorting algorithm design `binary_search_tree_sort` that processes an array of unsigned integers with a parameterizable size, ARRAY_SIZE (number of elements in the array, will be greater than 0). The st... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | binary_search_tree_sort | dut | [
{
"name": "binary_search_tree_sort.sv",
"content": "module binary_search_tree_sort #(\n parameter DATA_WIDTH = 32,\n parameter ARRAY_SIZE = 15\n) (\n input clk,\n input reset,\n input reg [ARRAY_SIZE*DATA_WIDTH-1:0] data_in, // Input data to be sorted\n input start,\n output reg [ARRAY_... | [] |
cvdp_copilot_secure_read_write_bus_0005 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `secure_read_write_bus_interface`. It support both read and write operations, with authorization based on a comparison between the input key and an internal parameterized key. The test bench should systematically generate input vectors, apply them to the m... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | secure_read_write_bus_interface | dut | [
{
"name": "secure_read_write_bus_interface.v",
"content": "module secure_read_write_bus_interface #(\n parameter p_configurable_key = 8'hAA, // Default key\n parameter p_data_width = 8, // Data width\n parameter p_addr_width = 8 // Address width\n)(\n input wir... | [] |
cvdp_copilot_cellular_automata_0002 | easy | Non-Agentic | Complete the given partial System Verilog testbench `tb_pseudoRandGenerator_ca`.The testbench must instantiate the `pseudoRandGenerator_ca` RTL module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `pseudoRandGenerator_ca` module simulates ... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | pseudoRandGenerator_ca | dut | [
{
"name": "pseudoRandGenerator_ca.sv",
"content": "module pseudoRandGenerator_ca (\n input logic clock, // Clock input\n input logic reset, // Active-high synchronous Reset\n input logic [15:0] CA_seed, // 16-bit Cellular Automata seed\n output logic [15:0] CA_out // 16-... | [] |
cvdp_agentic_hdbn_codec_0003 | medium | Agentic | The `hdbn_top` module's specification document is in the `docs/specification.md` folder. Write a SystemVerilog testbench, `tb_hdbn_top.sv`, in the `verif` directory to only generate stimulus for the `hdbn_top` module to achieve maximum coverage of the UUT.
Include the following in the generated testbench:
### 1. **Mo... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | hdbn_top | uut | [
{
"name": "hdbn_encoder.sv",
"content": "module hdbn_encoder\n(\n input logic reset_in, // Active high async reset\n input logic clk_in, // Rising edge clock\n input logic pulse_active_state, // Rising edge clock\n input logi... | [
{
"name": "specification.md",
"content": "# **HDBn (HDB3/HDB2) Codec Specification Document**\n\n## **1. Overview**\nThe HDBn (High-Density Bipolar) coding scheme was developed to solve critical issues in digital telecommunications transmission. Traditional AMI (Alternate Mark Inversion) coding faced proble... |
cvdp_copilot_hamming_code_tx_and_rx_0037 | easy | Non-Agentic | Develop a SystemVerilog testbench named `testbench_for_hamming_rx` to only supply stimuli to and achieve maximum possible coverage for an RTL design named `hamming_rx` . The module is a **parameterized Hamming code receiver** that takes an encoded input signal (`data_in`), which contains **data bits, parity bits, and ... | [
{
"inst_name": "uut_receiver",
"metric": "Overall Average",
"target_percentage": 97
}
] | hamming_rx | uut_receiver | [
{
"name": "hamming_rx.sv",
"content": "module hamming_rx \n#(\n parameter DATA_WIDTH = 4,\n parameter PARITY_BIT = 3,\n parameter ENCODED_DATA = PARITY_BIT + DATA_WIDTH + 1,\n parameter ENCODED_DATA_BIT = $clog2(ENCODED_DATA)\n)\n(\n input [ENCODED_DATA-1:0] data_in, \n output reg [DATA_WIDTH-1:0... | [] |
cvdp_agentic_direct_map_cache_0005 | medium | Agentic | I have a `direct_map_cache` module in the RTL directory. Write a SystemVerilog testbench named `tb_direct_map_cache.sv` in the verif directory that generates a wide range of read and write operations across different modes, such as compare and non-compare, and conditionally, like forced misses.
## Module Instance
- ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | direct_map_cache | uut | [
{
"name": "direct_map_cache.sv",
"content": "`timescale 1ns/1ps\nmodule direct_map_cache #(\n parameter CACHE_SIZE = 256, // Number of cache lines\n parameter DATA_WIDTH = 16, // Width of data\n parameter TAG_WIDTH = 5, // Width of the tag\n pa... | [] |
cvdp_copilot_concatenate_0003 | easy | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `enhanced_fsm_signal_processor` module by applying exhaustive test scenarios. The module uses a finite state machine (FSM) to manage signal processing operations, handle fault conditions, and report the FSM's current status. The test bench should systemati... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | enhanced_fsm_signal_processor | dut | [
{
"name": "enhanced_fsm_signal_processor.v",
"content": "// Verilog RTL Design for enhanced_fsm_signal_processor\n\nmodule enhanced_fsm_signal_processor (\n input wire i_clk, // Clock signal\n input wire i_rst_n, // Active-low reset signal\n input wire i_enable, // Enabl... | [] |
cvdp_copilot_digital_stopwatch_0017 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench`dig_stopwatch_tb`. The testbench must instantiate the `dig_stopwatch` RTL module and provide input stimulus to observe its behavior. This module implements a parameterized stopwatch with seconds, minutes, and hour tracking functionality. The testbench should include di... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 85
}
] | dig_stopwatch | uut | [
{
"name": "dig_stopwatch.sv",
"content": "module dig_stopwatch #(\n parameter CLK_FREQ = 50000000 // Default clock frequency is 50 MHz\n)(\n input wire clk, // Input clock (parameterized frequency)\n input wire reset, // Reset signal\n input wire start_stop, ... | [] |
cvdp_copilot_generic_nbit_counter_0013 | easy | Non-Agentic | Create a `tb_generic_counter` module that serves as the top-level testbench. This module should instantiate and include a `stimulus_generator` module, which must be developed to systematically drive different input conditions to the `generic_counter` module. The `stimulus_generator` should be designed to achieve 100% f... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | generic_counter | uut | [
{
"name": "generic_counter.sv",
"content": "\nmodule generic_counter #(parameter N = 8) (\n input logic clk_in, // Clock input\n input logic rst_in, // Active HIGH Reset input\n input logic [2:0] mode_in, // Mode input (3 bits)\n input logic enable_in, // Enable input\n... | [] |
cvdp_copilot_endian_swapper_0004 | medium | Non-Agentic | Develop a **SystemVerilog testbench** to generate **input stimulus** for the **`endian_swapper`** module with **DATA_BYTES = 8** (64-bit data). The testbench must systematically **apply input sequences** to exercise different functional behaviors of the DUT, ensuring that **all edge cases, control signals, and bufferin... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 92
}
] | endian_swapper | dut | [
{
"name": "endian_swapper.sv",
"content": "module endian_swapper #(\n parameter DATA_BYTES = 8\n) (\n input wire clk,\n input wire reset_n,\n\n input wire [(DATA_BYTES*8)-1:0] stream_in_data,\n input wire [$clog2(DATA_BYTES)-1:0] strea... | [] |
cvdp_copilot_signed_adder_0003 | medium | Non-Agentic | Create a stimulus generating test bench in SystemVerilog for a Verilog module named `signedadder` that add or subtract two signed 2's complement numbers, controlled by input signals and a state machine. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to ach... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | signedadder | dut | [
{
"name": "signedadder.v",
"content": "module signedadder #(parameter DATA_WIDTH = 8)(\n input i_clk,\n input i_rst_n,\n input i_start,\n input i_enable,\n input i_mode,\n input i_clear,\n input [DATA_WIDTH-1:0] i_operand_a,\n input [DATA_WIDTH-1:0] i_operand_b,\n output reg [DATA... | [] |
cvdp_agentic_dram_controller_0004 | hard | Agentic | I have a specification of a `dramcntrl` module in the `docs` directory. Write a SystemVerilog testbench `dramcntrl_tb.sv` in the `verif` directory to only generate stimuli and achieve maximum functional coverage for the `dramcntrl` module.
Include the following in the generated testbench:
- **Module Instance**: Insta... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 92
}
] | dramcntrl | dut | [
{
"name": "dramcntrl.sv",
"content": "`timescale 1ns / 1ps\n\nmodule dramcntrl \n#(\n //==========================================================================\n // Parameters\n //==========================================================================\n parameter integer del ... | [
{
"name": "specs.md",
"content": "## Overview\n\nAn SDRAM controller that manages DRAM initialization, auto-refresh, and read/write operations. It uses counters, state machines, and vector arithmetic (`incr_vec`/`dcr_vec`) to schedule commands and generate DRAM control signals (`addr`, `ba`, `clk`, `cke`, `... |
cvdp_copilot_csr_using_apb_0005 | medium | Non-Agentic | Write a SystemVerilog testbench to only generate stimulus for a `csr_apb_interface` module, which is responsible for data transactions over the Advanced Peripheral Bus (APB) interface.
## Interface: **csr_using_apb**
**Clock & Reset**:
`pclk`: APB clock input for synchronous operations.
`presetn`: Active-low asynchro... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | csr_apb_interface | uut | [
{
"name": "csr_apb_interface.sv",
"content": "`timescale 1ns / 1ps\nmodule csr_apb_interface (\n input pclk, // Clock input for synchronization\n input presetn, // Active-low asynchronous reset input\n input [31:0] paddr, ... | [] |
cvdp_copilot_32_bit_Brent_Kung_PP_adder_0004 | medium | Non-Agentic | Complete the given partial System Verilog testbench `tb_brent_kung_adder`. The testbench must instantiate the `brent_kung_adder` RTL module and provide input stimulus for it focusing exclusively on generating comprehensive test vectors rather than building a full testbench. A Brent Kung Adder is a parallel prefix adder... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | brent_kung_adder | uut | [
{
"name": "brent_kung_adder.sv",
"content": "module brent_kung_adder(\n input logic [31:0] a,\n input logic [31:0] b,\n input logic carry_in,\n output logic [31:0] sum,\n output logic carry_out\n);\n logic [31:0] P1, G1;\n logic [32:1] C;\n logic [15:0] G2, P2;\n logic [7:0] G3... | [] |
cvdp_agentic_door_lock_0003 | medium | Agentic | I have a specification of a `door_lock` module in the `docs` directory. Write a SystemVerilog testbench `tb_door_lock.sv` in the `verif` directory to only generate stimuli and achieve maximum coverage for the `door_lock` module.
Include the following in the generated testbench:
- **Module Instance**: Instantiate the ... | [
{
"inst_name": "door_lock_inst",
"metric": "Overall Average",
"target_percentage": 95
}
] | door_lock | door_lock_inst | [
{
"name": "door_lock.sv",
"content": "module door_lock #(\n parameter PASSWORD_LENGTH = 4, // Number of digits in the password\n parameter MAX_TRIALS = 4 // Maximum allowed incorrect attempts\n) (\n input logic clk , // Clock signal\n input logic ... | [
{
"name": "specification.md",
"content": "# Door Lock System Specification Document\n\n## **Introduction**\nThe **Door Lock System** is a password-protected authentication module designed for **PIN-based access control** with a configurable password length. The module provides user authentication through pa... |
cvdp_copilot_secure_variable_timer_0006 | medium | Non-Agentic | Create a self-checking test bench in SystemVerilog for a Verilog module named `secure_variable_timer`. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as *... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | secure_variable_timer | dut | [
{
"name": "secure_variable_timer.v",
"content": "module secure_variable_timer (\n input wire i_clk, // Clock signal (rising-edge triggered)\n input wire i_rst_n, // Active-low synchronous reset signal\n input wire i_data_in, // Serial data input\n output... | [] |
cvdp_copilot_IIR_filter_0016 | medium | Non-Agentic | Create a SystemVerilog testbench module named **`iir_filter_tb`** that instantiates the `iir_filter` module and applies stimulus to the instantiated module for different test scenarios.
---
### **Inputs**
- **Clock Signal**:
- `clk`: Positive edge-triggered clock signal driving the IIR filter.
- **Reset Sig... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | iir_filter | dut | [
{
"name": "iir_filter.sv",
"content": "module iir_filter (\n input logic clk,\n input logic rst,\n input logic signed [15:0] x, // Input sample\n output logic signed [15:0] y // Output sample\n);\n\n // Filter coefficients\n parameter signed [15:0] b0 = 16'h0F00;\n parameter signe... | [] |
cvdp_copilot_gcd_0028 | easy | Non-Agentic | Write a testbench to only generate stimulus for a `gcd_3_ip` that calculates the greatest common divisor (GCD) for three signed inputs, using the Euclidean algorithm, and generates the output `OUT` and `done` sequentially when `go` is asserted and inputs `A`, `B` and `C` are applied. In this design, the `OUT` output is... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | gcd_3_ip | dut | [
{
"name": "gcd_top.sv",
"content": "`timescale 1ns/1ps\nmodule gcd_3_ip #(\n parameter WIDTH = 32,\n parameter SIGNED_EN = 1\n )(\n input clk,\n input rst,\n input [WIDTH-1:0] A,\n input [WIDTH-1:0] B,\n input [WIDTH-1:0] C,\n ... | [] |
cvdp_copilot_single_cycle_arbiter_0004 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `single_cycle_arbiter` module. This module implements a **fixed-priority, single-cycle arbitration** mechanism that grants exactly one request per cycle based on a priority scheme where **Port 0 has the highest priority** and **Port N-1 has the lowest priority**. The ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 96
}
] | single_cycle_arbiter | uut | [
{
"name": "single_cycle_arbiter.sv",
"content": "module single_cycle_arbiter #(\n parameter N = 32\n) (\n input logic clk,\n input logic reset,\n input logic [N-1:0] req_i,\n output logic [N-1:0] gnt_o\n);\n\n // --------------------------------------------------------\n //... | [] |
cvdp_copilot_IIR_filter_0012 | medium | Non-Agentic | Complete the Given Partial SystemVerilog Testbench `iir_filt_tb`. The testbench must instantiate the `iir_filt` RTL module and provide input stimulus for it, focusing exclusively on generating comprehensive test vectors rather than building a full testbench. The IIR filter processes three input signals and outputs thre... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | iir_filt | uut | [
{
"name": "iir_filt.sv",
"content": "module iir_filt #(parameter WIDTH = 16)(\n input clk,\n input reset,\n input signed [WIDTH-1:0] in_1,\n input signed [WIDTH-1:0] in_2,\n input signed [WIDTH-1:0] in_3,\n input [1:0] filter_select, // 00: Butterworth, 01: Chebyshev, 10: Elliptic\n out... | [] |
cvdp_copilot_skid_register_0004 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `skid_register` module. This module serves as a pipeline register with a skid buffer to handle backpressure. The testbench must simulate various scenarios to verify data flow, handshake mechanisms, and buffer operations.
---
### **Inputs:**
- `clk`: **1-bit clock s... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | skid_register | dut | [
{
"name": "skid_register.sv",
"content": "module skid_register\n #(parameter DATA_WIDTH = 32)\n(\n input wire clk,\n input wire rst,\n\n // Upstream (source) side\n input wire [DATA_WIDTH-1:0] up_bus,\n input wire up_val,\n ... | [] |
cvdp_copilot_asyc_reset_0004 | easy | Non-Agentic | Create a **testbench** to apply **stimulus** to the `async_reset` module. This module implements an asynchronous reset mechanism along with a countdown counter. The counter initializes to `5'h1F` upon reset and decrements on each clock cycle until reaching zero. The module also provides gated clock and reset release si... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | async_reset | dut | [
{
"name": "async_reset.sv",
"content": "module async_reset (\n input logic clk,\n input logic reset,\n\n output logic release_reset_o,\n output logic gate_clk_o,\n output logic [4:0] cnt_q\n);\n\n// --------------------------------------------------------\n// Asynchr... | [] |
cvdp_copilot_nbit_swizzling_0009 | easy | Non-Agentic | Write a SystemVerilog testbench for a `nbit_swizzling` module that performs bitwise operations on input data based on a selection signal(`sel`). The testbench should only provide a sequence of test cases to the instantiated RTL module for nbit-swizzling transformations based on the selection signal and ensure proper sy... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | nbit_swizzling | uut | [
{
"name": "nbit_swizzling.sv",
"content": "module nbit_swizzling #(parameter DATA_WIDTH = 64)(\n input [DATA_WIDTH-1:0] data_in, // Input data of size DATA_WIDTH \n input [1:0] sel, \t // 2-bit selection signal ... | [] |
cvdp_copilot_hill_cipher_0012 | easy | Non-Agentic | Create a testbench to generate the stimuli for the `hill_cipher` module, which applies a 3×3 key matrix to a 3-letter (15-bit) plaintext vector, computing the ciphertext (also 3 letters, 15 bits) modulo 26.
---
## Description
### Inputs
- **Registers**:
- `clk (1 bit)`: Clock signal that drives the internal finit... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | hill_cipher | uut | [
{
"name": "hill_cipher.sv",
"content": "`timescale 1ns/1ps\n\nmodule hill_cipher (\n input logic clk,\n input logic reset,\n input logic start,\n input logic [14:0] plaintext, // 3 letters, 5 bits each\n input logic [44:0] key, // 9 elements, 5 bits each\n output logic [14:0] cip... | [] |
cvdp_copilot_matrix_multiplier_0022 | easy | Non-Agentic | Write a testbench for the `matrix_multiplier` module, which performs matrix multiplication for configurable dimensions. The testbench should focus only on generating stimuli to exercise all key features of the module.
---
## Design Details
### **Parameterization**
1. **ROW_A**: Number of rows in Matrix A. (Default=4... | [
{
"inst_name": "matrix_multiplier_inst",
"metric": "Overall Average",
"target_percentage": 100
}
] | matrix_multiplier | matrix_multiplier_inst | [
{
"name": "matrix_multiplier.sv",
"content": "module matrix_multiplier #(\n parameter ROW_A = 4 , // Number of rows in matrix A\n parameter COL_A = 4 , // Number of columns in matrix... | [] |
cvdp_agentic_bcd_adder_0006 | easy | Agentic | I have a `bcd_adder` module implemented in the RTL directory. Write a SystemVerilog testbench `tb_bcd_adder.sv` in the verif directory that generates stimuli to thoroughly test and achieve maximum coverage for the bcd_adder module.
Include the following in the generated testbench:
### Module Instance
Instantiate the ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | bcd_adder | uut | [
{
"name": "four_bit_adder.sv",
"content": "//module of four_bit_adder\nmodule four_bit_adder( \n input [3:0] a, // 4-bit input a\n input [3:0] b, // 4-bit input b\n input cin, // Carry input\n ... | [
{
"name": "bcd_adder_spec.md",
"content": "# BCD Adder Module (bcd_adder)\n\nThis module adds two 4-bit BCD numbers and ensures the result remains in valid BCD form (0–9 per digit). It first detects invalid inputs (values above 9) and clamps them to 9 before performing the addition. If the intermediate resu... |
cvdp_copilot_decode_firstbit_0017 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `cvdp_copilot_decode_firstbit` module. This module detects the first set bit in a **32-bit binary input** and outputs its position in either **binary or one-hot encoding**. The testbench must generate a diverse set of input patterns while ensuring compliance with the ... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
}
] | cvdp_copilot_decode_firstbit | dut | [
{
"name": "cvdp_copilot_decode_firstbit.sv",
"content": "module cvdp_copilot_decode_firstbit #(\n parameter integer InWidth_g = 32,\n parameter InReg_g = 1,\n parameter OutReg_g = 1,\n parameter integer PlRegs_g = 1,\n parameter OutputFormat_g = 0 // 0: Binary, 1: One-Hot Encoding\n)(\n i... | [] |
cvdp_copilot_cdc_pulse_synchronizer_0017 | easy | Non-Agentic | Complete the given SystemVerilog testbench for the `cdc_pulse_synchronizer` module. The testbench currently instantiates the UUT and should include a stimulus generator (`stimulus_generator`) that dynamically produces a wide range of test scenarios to ensure 100% functional and code coverage. The stimulus generator sho... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | cdc_pulse_synchronizer | uut | [
{
"name": "cdc_pulse_synchronizer.sv",
"content": "module cdc_pulse_synchronizer (\n input logic src_clock, // Source Clock Domain\n input logic des_clock, // Destination Clock Domain\n input logic rst_in, // Reset\n input logic src_pulse, // Source Pulse\n output logic des_pul... | [] |
cvdp_copilot_Attenuator_0011 | easy | Non-Agentic | Create a testbench for the `Attenuator` module, which takes a 5-bit input (`data`) and shifts it out serially after detecting changes, finally latching with `ATTN_LE`.
---
## Description
### Inputs
- **Registers**:
- `clk (1 bit)`: Clock signal driving the state machine and internal half-rate clock generation (`c... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | Attenuator | uut | [
{
"name": "Attenuator.sv",
"content": "`timescale 1ns / 1ps\n\nmodule Attenuator (\n input clk,\n input reset,\n input [4:0] data,\n output reg ATTN_CLK,\n output reg ATTN_DATA,\n output reg ATTN_LE\n);\n\nreg clk_div2;\nreg [1:0] current_state, next_state;\nreg [... | [] |
cvdp_copilot_gray_to_binary_0014 | easy | Non-Agentic | Create a testbench for the `gray_to_binary` module, which converts an N-bit Gray code input into its N-bit binary equivalent using combinational logic. The testbench must have the instantiation of RTL module and generate stimulus for various test conditions.
### Interface of gray_to_binary RTL Module
**Parameter:**
... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | gray_to_binary | uut | [
{
"name": "gray_to_binary.sv",
"content": "`timescale 1ns / 1ps\n\nmodule gray_to_binary #(\n parameter WIDTH = 4\n) (\n input logic [WIDTH-1:0] gray_in, // Gray code input\n output logic [WIDTH-1:0] binary_out // Binary output\n);\n\n always @* begin\n binary_out[WIDTH-1] = gray_in[WIDTH-... | [] |
cvdp_copilot_word_change_detector_0012 | medium | Non-Agentic | Complete the Given Partial System Verilog Testbench `tb_Word_Change_Pulse`. The testbench must instantiate the `Word_Change_Pulse` RTL module and provide input stimulus to validate its behavior. This module detects word changes and pattern matches in a DATA_WIDTH-bit data stream based on a specified mask and pattern.
... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | Word_Change_Pulse | uut | [
{
"name": "Word_Change_Pulse.sv",
"content": "// Word_Change_Pulse Module with Maskable Input, Pattern Matching, and Advanced Features\nmodule Word_Change_Pulse #(\n parameter DATA_WIDTH = 8 // Default word width\n) (\n input wire clk, // Clock signal for synchronizing ... | [] |
cvdp_copilot_image_stego_0014 | medium | Non-Agentic | Develop a SystemVerilog module named `tb_image_stego` that generates input stimulus to verify the `image_stego` module. The `image_stego` module embeds bits of data into an image. Each pixel is 8 bits, and up to 4 bits can be embedded according to a `mask` control. The data bits are first XOR-encrypted by an 8-bit key.... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | image_stego | uut | [
{
"name": "image_stego.sv",
"content": "`timescale 1ns/1ps\nmodule image_stego #(\n parameter row = 2,\n parameter col = 2,\n parameter EMBED_COUNT_WIDTH = 3\n)(\n input [(row*col*8)-1:0] img_in,\n input [(row*col*4)-1:0] data_in,\n input [2:0] bpp,\n input [7:0] encryption_key,\n input [(row*col)-1... | [] |
cvdp_copilot_sobel_filter_0015 | easy | Non-Agentic | Write a SystemVerilog testbench for a Sobel filter module named `sobel_filter` that performs edge detection on a stream of pixel data. The Sobel filter calculates the gradient magnitude using a 3x3 pixel window and determines whether the edge strength exceeds a predefined threshold `THRESHOLD`. The testbench should onl... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | sobel_filter | dut | [
{
"name": "sobel_filter.sv",
"content": "module sobel_filter (\n input logic clk,\n input logic rst_n,\n input logic [7:0] pixel_in,\n input logic valid_in,\n output logic [7:0] edge_out,\n output logic valid_out\n);\n \n logic s... | [] |
cvdp_copilot_fixed_arbiter_0004 | easy | Non-Agentic | Write a SystemVerilog testbench to generate stimulus for the `fixed_priority_arbiter` module. The testbench should validate the priority-based grant mechanism by applying different request patterns, including single, multiple, and no request scenarios. Additionally, it should verify the reset functionality and ensure t... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | fixed_priority_arbiter | dut | [
{
"name": "fixed_priority_arbiter.sv",
"content": "`timescale 1ns / 1ps\n\nmodule fixed_priority_arbiter(\n input clk, // Clock signal\n input reset, // Active high reset signal\n input [7:0] req, // 8-bit request signal; each bit represents a request from a different so... | [] |
cvdp_agentic_spi_complex_mult_0008 | medium | Agentic | Design a SystemVerilog testbench, `spi_complex_mult_tb.sv`, in the verif directory to only generate stimulus and achieve maximum coverage for the module on the file in `rtl/spi_complex_mult.sv`. Refer to the specification in `docs/specification.md`, which defines a SPI Slave that receives the complex number components... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | spi_complex_mult | dut | [
{
"name": "spi_complex_mult.sv",
"content": "module spi_complex_mult #(\n parameter IN_WIDTH = 'd16, // Parameter defining the input width\n parameter OUT_WIDTH = 'd32 // Parameter defining the output width\n) (\n input logic rst_async_n, // Asynchronous reset signal, active low... | [
{
"name": "specification.md",
"content": "# SPI Slave Complex Multiplication Specification\n\n## Overview\nThe `spi_complex_mult` module implements a SPI Slave module that receives the complex number components Ar, Ai, Br, and Bi (real and imaginary parts) via SPI and performs complex multiplication using D... |
cvdp_copilot_secure_read_write_register_bank_0006 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `secure_read_write_register_bank`. It allows read and write operations only after unlocking, which requires specific values written to the first two addresses in sequence.The test bench should systematically generate input vectors, apply them to the module... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 96
}
] | secure_read_write_register_bank | dut | [
{
"name": "secure_read_write_register_bank.v",
"content": "// -----------------------------------------------------------------------------\n// Module Name: secure_read_write_register_bank\n// Description: \n// This module implements a secure, parameterized register bank with access \n// control. It uses a ... | [] |
cvdp_agentic_search_algorithm_0001 | medium | Agentic | I have a specification of a `linear_search_top` module in the `docs` directory. Write a SystemVerilog testbench `tb_linear_search.sv` in the `verif` directory to only generate stimulus for the `linear_search_top` module and achieve maximum coverage of the design.
Include the following in the generated testbench:
- **... | [
{
"inst_name": "linear_search_top_inst",
"metric": "Overall Average",
"target_percentage": 100
},
{
"inst_name": "datapath",
"metric": "Overall Average",
"target_percentage": 100
},
{
"inst_name": "ctrl",
"metric": "Overall Average",
"target_percentage": 100
}
] | linear_search_top | linear_search_top_inst | [
{
"name": "linear_search_datapath.sv",
"content": "module linear_search_datapath #(\n parameter DATA_WIDTH = 8 ,\n parameter ADDR_WIDTH = 4 ,\n parameter MEM_DEPTH = 1 << ADDR_WIDTH, // Total memory size\n parameter MAX_MATCHES = 8 // Max number of indices ... | [
{
"name": "specification.md",
"content": "# Linear Search Engine Specification Document\n\n## **Introduction**\nThe **Linear Search Engine** is a parameterized, hierarchical RTL design that performs a **linear search** over a memory array to find all locations where a given key matches stored data. It suppo... |
cvdp_copilot_wb2ahb_0004 | medium | Non-Agentic | Write a System Verilog testbench to generate stimulus for a `wishbone_to_ahb_bridge_tb` module, which is responsible for bridging transactions between a Wishbone master and an AHB slave.
## **Design Specification**
The `wishbone_to_ahb_bridge` module serves as a bridge between the Wishbone bus and the AMBA AHB bus, f... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | wishbone_to_ahb_bridge | uut | [
{
"name": "wishbone_to_ahb_bridge.sv",
"content": "`timescale 1ns / 1ps\n\nmodule wishbone_to_ahb_bridge\n // Wishbone ports from WB master\n (\n input clk_i, // Clock input for Wishbone\n input rst_i, // Reset input for Wishbone\n input cyc_i, // Cycle signal from... | [] |
cvdp_copilot_adc_data_rotate_0009 | easy | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `adc_data_rotate` module by applying exhaustive test scenarios. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage. The testbench should not creat... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 92
}
] | adc_data_rotate | dut | [
{
"name": "adc_data_rotate.sv",
"content": "module adc_data_rotate #(\n parameter DATA_WIDTH = 8 // Parameterized data width (default = 8)\n)(\n // Inputs\n input logic i_clk, // Clock signal\n input logic i_rst_n, // Active-low res... | [] |
cvdp_copilot_Synchronous_Muller_C_Element_0003 | easy | Non-Agentic | Write a SystemVerilog testbench to only generate stimulus for a `sync_muller_c_element` design with configurable inputs and pipeline depth. This design processes input signals through a configurable pipeline and produces a single-bit output based on the state of the inputs in the final pipeline stage, outputting 1 only... | [
{
"inst_name": "sync_muller_c_element_inst",
"metric": "Overall Average",
"target_percentage": 100
}
] | sync_muller_c_element | sync_muller_c_element_inst | [
{
"name": "sync_muller_c_element.sv",
"content": "module sync_muller_c_element #(\n parameter NUM_INPUT = 2, // Number of input signals\n parameter PIPE_DEPTH = 1 // Number of pipeline stages\n) (\n input logic clk , // Clock signal\n input logic srst , // Synchr... | [] |
cvdp_agentic_helmholtz_0003 | medium | Agentic | The specification document for the `helmholtz_top_module` is present in the `docs` folder. Write a SystemVerilog testbench, `helmholtz_top_module_tb.sv`, in the `verif` directory to only generate stimulus for the `helmholtz_top_module` to achieve maximum coverage of the DUT.
Include the following in the generated test... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
}
] | helmholtz_top_module | dut | [
{
"name": "helmholtz_top_module.sv",
"content": "module helmholtz_resonator #(\n parameter WIDTH = 16,\n parameter FRAC_BITS = 8,\n parameter CAL_TOLERANCE = 10 // 10% tolerance //\n)(\n input logic clk,\n input logic rst,\n input logic calibrate,\n input logic signed [WIDTH-1:0] audio_... | [
{
"name": "specs_tb.md",
"content": "# Helmholtz Resonator Audio Processor Specification Document\n\n## Introduction\n\nThe **Helmholtz Resonator Audio Processor** is a pipelined and modular Verilog design intended for real-time audio signal processing. It is inspired by acoustic resonance principles and de... |
cvdp_copilot_ping_pong_buffer_0004 | easy | Non-Agentic | Complete the Ping-Pong Buffer Testbench in SystemVerilog. The testbench must instantiate the `ping_pong_buffer` RTL module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `ping_pong_buffer` module simulates a dual-buffer system that allows ... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | ping_pong_buffer | dut | [
{
"name": "ping_pong_buffer.sv",
"content": "module ping_pong_buffer (\n input logic clk,\n input logic rst_n,\n input logic write_enable,\n input logic read_enable,\n input logic [7:0] data_in,\n output logic [7:0] data_out,\n output logic buffer_full,\n output logic buffer_empty,\n... | [] |
cvdp_copilot_hebbian_rule_0020 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_hebb_gates` that instantiates the `hebb_gates` module as the Unit Under Test (UUT). The testbench must include a stimulus generator that systematically drives various input conditions to achieve a minimum of 95% code and functional coverage for the `hebb_gates` module. ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | hebb_gates | uut | [
{
"name": "hebb_gates.sv",
"content": "`timescale 1ns/1ps\nmodule hebb_gates(\n input logic clk, // Posedge clk\n input logic rst, // Asynchronous negedge rst\n input logic start, // To start the FSM\n input logic [1:0] t... | [] |
cvdp_copilot_sync_serial_communication_0009 | easy | Non-Agentic | Write a SystemVerilog testbench for a `sync_serial_communication_tx_rx` module, which simulates the `tx_block` and `rx_block` modules and performs data transfer operations with a focus on ensuring the proper handling of data values, selection signals(`sel`), and asynchronous resets. The testbench must apply a sequence ... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | sync_serial_communication_tx_rx | uut | [
{
"name": "sync_serial_communication_top.sv",
"content": "`timescale 1ns / 1ps\nmodule sync_serial_communication_tx_rx(\n input clk, // Clock signal\n input reset_n, // Active low reset signal\n input [2:0] sel, // Selection signal for TX block\n ... | [] |
cvdp_copilot_hamming_code_tx_and_rx_0029 | easy | Non-Agentic | Create a testbench that only supplies stimulus to a `hamming_code_tx_for_4bit` module, which encodes 4-bit input data `data_in` into an 8-bit output `data_out` using Hamming code principles for error detection and correction. Hamming code helps generate parity bits, which are combined with the original data to detect a... | [
{
"inst_name": "uut_transmitter",
"metric": "Overall Average",
"target_percentage": 91
}
] | hamming_code_tx_for_4bit | uut_transmitter | [
{
"name": "hamming_code_tx_for_4bit.sv",
"content": "module hamming_code_tx_for_4bit( \n input[3:0] data_in,\n output[7:0] data_out\n);\n assign data_out[0] = 1'b0;\n assign data_out[1] = data_in[0] ^ data_in[1] ^ data_in[3]; // 2^0\n assign data_out[2] = data_in[0] ^ data_in[2] ^ data_in[3]; // 2^1\n ... | [] |
cvdp_copilot_sram_fd_0024 | easy | Non-Agentic | Generate a SystemVerilog testbench named `cvdp_sram_fd_tb` that only generates stimulus, to systematically drive input signals to a **cvdp_sram_fd** module. The stimulus should comprehensively cover all valid read and write operations with constraints as mentioned below.
---
## Module Overview:
The **cvdp_sram_fd** ... | [
{
"inst_name": "DUT",
"metric": "Overall Average",
"target_percentage": 100
}
] | cvdp_sram_fd | DUT | [
{
"name": "cvdp_sram_fd.sv",
"content": "/**************************************************************************\nFILENAME: cvdp_sram_fd.sv\nDESCRIPTION: This file contains the RTL for a full-duplex dual-port RAM in SystemVerilog.\nLATENCY: Write latency = 1 clk cycle\n Read latency ... | [] |
cvdp_copilot_MSHR_0003 | medium | Non-Agentic | Develop a SystemVerilog module named `tb_cache_mshr` that only generates input stimulus to a `cache_mshr` module. `cache_mshr` module implements Miss Status Handling Registers (MSHR). The MSHR is a critical component of a **non-blocking cache architecture**, enabling the system to handle multiple outstanding cache miss... | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | cache_mshr | dut | [
{
"name": "cache_mshr.sv",
"content": "`define NOTCONNECTED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \\\n . x () \\\n /* verilator lint_on PINCONNECTEMPTY */\n\nmodule cache_mshr #(\n parameter INSTANCE_ID = \"mo_mshr\" ,\n ... | [] |
cvdp_agentic_rgb_color_space_conversion_0009 | medium | Agentic | The specification document for the `rgb_color_space_conversion` module is present in the `docs` folder. Write a SystemVerilog testbench, `tb_rgb_color_space_conversion.sv`, in the `verif` directory to only generate stimulus for the `rgb_color_space_conversion` module to achieve maximum coverage of the UUT.
Include the... | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | rgb_color_space_conversion | uut | [
{
"name": "rgb_color_space_conversion.sv",
"content": "module rgb_color_space_conversion (\n input clk,\n input rst,\n\n // Memory ports to initialize (1/delta) values\n input we,\n input [7:0] waddr,\n input [24:0] wdata,\n\n // ... | [
{
"name": "specification.md",
"content": "# RGB to HSV/HSL Conversion Module Specification Document\n\n## Introduction\n\nThe **RGB to HSV/HSL Conversion Module** is designed to convert RGB (Red, Green, Blue) color space values into both HSV (Hue, Saturation, Value) and HSL (Hue, Saturation, Lightness) colo... |
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