code stringlengths 144 85.5k | apis sequence | extract_api stringlengths 121 59.8k |
|---|---|---|
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------... | [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((3780, 3894), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-UV4LQ144C6/I5"""', '_io', '_connectors'], {'toolchain': 'toolchain', 'devicename': '"""GW1N-4"""'}), "(self, 'GW1N-UV4LQ144C6/I5', _io, _connectors,\n toolchain=toolchain, devicename='GW1N-4')\n", (3802,... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2017-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ---------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((18029, 18124), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xcku040-ffva1156-2-e"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xcku040-ffva1156-2-e', _io, _connectors,\n toolchain='vivado')\n", (18052, 18124), False, 'from litex.build.xilinx import ... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Board diagram/pinout:
# https://user-images.githubusercontent.com/1450143/133655492-532d5e9a-0635-4889-85c9-68683d06cae0.png
# http://dl.sipeed.com/TANG/Nano/HDK/Tang-NANO-2704(Schematic).pdf
from ... | [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((1481, 1592), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-LV1QN48C6/I5"""', '_io', '_connectors'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1N-1"""'}), "(self, 'GW1N-LV1QN48C6/I5', _io, _connectors,\n toolchain='gowin', devicename='GW1N-1')\n", (1503, 1... |
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 msloniewski <<EMAIL>>
# Copyright (c) 2019 vytautasb <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import subprocess
import sys
import math
from shutil import which
from migen.fhdl.structure import _Fragmen... | [
"litex.build.tools.get_litex_git_revision",
"litex.build.generic_platform.Pins",
"litex.build.tools.write_to_file"
] | [((6393, 6459), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(True)'}), '(script_file, script_contents, force_unix=True)\n', (6412, 6459), False, 'from litex.build import tools\n'), ((6627, 6647), 'shutil.which', 'which', (['"""quartus_map"""'], {}), "('... |
#!/usr/bin/env python3
import time
from statistics import mean
from litex import RemoteClient
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
# # #
# Read frequency meter
fmeter_values = []
print("Reading frequency...")
for i in range(100):
fmeter_value = wb.regs.fmeter_value.read()
print(fmeter_value)... | [
"litex.RemoteClient"
] | [((102, 138), 'litex.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (114, 138), False, 'from litex import RemoteClient\n'), ((364, 379), 'time.sleep', 'time.sleep', (['(1.0)'], {}), '(1.0)\n', (374, 379), False, 'import time\n'), ((398, 417), 'statistics.mean', 'me... |
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from bft import Bft
from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface
from litex.soc.interconnect.stream import (ClockDomainCrossing, Converter,
Endpoint)
from migen import *
from pld_ax... | [
"litex.soc.interconnect.axi.AXILiteInterface"
] | [((5719, 5794), 'litex.soc.interconnect.axi.AXILiteInterface', 'AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(5)', 'clock_domain': 'clock_domain'}), '(data_width=32, address_width=5, clock_domain=clock_domain)\n', (5735, 5794), False, 'from litex.soc.interconnect.axi import AXILiteInterface, AXIStre... |
from litex.tools.litex_client import RemoteClient
wb = RemoteClient("192.168.1.50", 1234, csr_data_width=8)
wb.open()
regs = wb.regs
# # #
print("temperature: %f°C" %(regs.xadc_temperature.read()*503.975/4096 - 273.15))
print("vccint: %fV" %(regs.xadc_vccint.read()/4096*3))
print("vccaux: %fV" %(regs.xadc_vccaux.rea... | [
"litex.tools.litex_client.RemoteClient"
] | [((56, 108), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', (['"""192.168.1.50"""', '(1234)'], {'csr_data_width': '(8)'}), "('192.168.1.50', 1234, csr_data_width=8)\n", (68, 108), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import csv
import logging
import argparse
from operator import and_
from functools import reduce
from itertools import zip_longest
from migen import *
from migen.genlib.misc import WaitTimer
from litex.build.sim.config import S... | [
"litex.tools.litex_sim.SimSoC.__init__",
"litex.build.sim.config.SimConfig"
] | [((7932, 8004), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteDRAM Benchmark SoC Simulation"""'}), "(description='LiteDRAM Benchmark SoC Simulation')\n", (7955, 8004), False, 'import argparse\n'), ((9954, 9973), 'logging.getLogger', 'logging.getLogger', ([], {}), '()\n', (9971, 9973... |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
rom_base = 0x00000000
dump_size = 0x8000
words_per_packet = 128
wb = RemoteClient()
wb.open()
# # #
print("dumping cpu rom to dump.bin...")
dump = []
for n in range(dump_size//(words_per_packet*4)):
dump += wb.read(rom_base + n*words_per_p... | [
"litex.tools.litex_client.RemoteClient"
] | [((144, 158), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (156, 158), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020-21 gatecat <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSy... | [
"litex.soc.interconnect.wishbone.SRAM",
"litex.build.lattice.oxide.oxide_args",
"litex.soc.cores.ram.NXLRAM",
"litex.soc.cores.freqmeter.FreqMeter",
"litex.soc.cores.gpio.GPIOIn",
"litex.build.lattice.oxide.oxide_argdict"
] | [((7015, 7089), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Crosslink-NX VIP Board"""'}), "(description='LiteX SoC on Crosslink-NX VIP Board')\n", (7038, 7089), False, 'import argparse\n'), ((7766, 7784), 'litex.build.lattice.oxide.oxide_args', 'oxide_args', (['parser'], ... |
#
# This file is part of LiteX.
#
# Copyright (c) 2016-2017 <NAME> <<EMAIL>>
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
IBM's 8b/10b Encoding
This scheme is used by a large number of protocols including Display Port, PCI
Express, Gigabit Ethernet, SATA and USB 3.
The encod... | [
"litex.soc.interconnect.stream.PipelinedActor.__init__",
"litex.soc.interconnect.stream.Endpoint"
] | [((10573, 10624), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('d', nwords * 8), ('k', nwords)]"], {}), "([('d', nwords * 8), ('k', nwords)])\n", (10588, 10624), False, 'from litex.soc.interconnect import stream\n'), ((10654, 10694), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.cs... | [
"litex.build.sim.SimPlatform.__init__",
"litex.build.generic_platform.Pins"
] | [((908, 928), 'litedram.phy.utils.Serializer', 'Serializer', ([], {}), '(**kwargs)\n', (918, 928), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((1174, 1196), 'litedram.phy.utils.Deserializer', 'Deserializer', ([], {}), '(**kwargs)\n', (1186, 1196), False, 'from litedram.phy.utils import S... |
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((3739, 3789), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE22F17C6"""', '_io'], {}), "(self, 'EP4CE22F17C6', _io)\n", (3762, 3789), False, 'from litex.build.altera import AlteraPlatform\n'), ((3839, 3851), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ---------------------------------------------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((2536, 2586), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE15F23C8"""', '_io'], {}), "(self, 'EP4CE15F23C8', _io)\n", (2559, 2586), False, 'from litex.build.altera import AlteraPlatform\n'), ((2636, 2648), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs -------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((4685, 4759), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', 'device', 'io', 'connectors'], {'toolchain': 'toolchain'}), '(self, device, io, connectors, toolchain=toolchain)\n', (4708, 4759), False, 'from litex.build.altera import AlteraPlatform\n'), ((5037, 5049), 'litex.build.alt... |
from migen import Module, Signal, Instance, ClockDomain, If
from litex.build.lattice.platform import LatticePlatform
from litex.soc.cores import up5kspram, spi_flash
from litex_boards.targets.fomu import _CRG
import litex.soc.doc as lxsocdoc
import spibone
from ..romgen import RandomFirmwareROM, FirmwareROM
from .... | [
"litex.soc.cores.up5kspram.Up5kSPRAM",
"litex.build.lattice.platform.LatticePlatform.__init__"
] | [((3049, 3059), 'litex_boards.targets.fomu._CRG', '_CRG', (['self'], {}), '(self)\n', (3053, 3059), False, 'from litex_boards.targets.fomu import _CRG\n'), ((3371, 3407), 'litex.soc.cores.up5kspram.Up5kSPRAM', 'up5kspram.Up5kSPRAM', ([], {'size': 'spram_size'}), '(size=spram_size)\n', (3390, 3407), False, 'from litex.s... |
# Support for the Digilent Atlys (http://digilentinc.com/atlys/) - The board used for HDMI2USB prototyping.
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, iMPACT
# There appear to be 4 x LTC2481C on the U1-SCL / U1-SDA lines connected to the Cypress
class DynamicLVCMOS(obje... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.iMPACT",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((37550, 37618), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx45-csg324-3"""', '_io', '_connectors'], {}), "(self, 'xc6slx45-csg324-3', _io, _connectors)\n", (37573, 37618), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38798, 38840), 'litex.build.... |
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.openocd import OpenOCD
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("H5"), IOSt... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.VivadoProgrammer"
] | [((4558, 4633), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-csg324-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a35t-csg324-1', _io, toolchain=toolchain)\n", (4581, 4633), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'),... |
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